1. Field of the Invention
The present invention relates to a protection circuit section for protecting a protection target in a semiconductor circuit system from a surge. Typically, the protection circuit section employs a silicon controlled rectifier (SCR) to protect a protection target from electro-static discharge (ESD). For example, the protection circuit section is applied to a CMOS-LSI of the low power supply voltage type.
2. Description of the Related Art
There is a known technique in which an ESD protection circuit is connected to the input circuit or output circuit of a CMOS-LSI to protect it from ESD breakdown. The ESD protection circuit employs a protection element, such as a diode, transistor, or SCR.
Generally, in an ESD protection circuit employing an SCR, the operation voltage of the SCR is high. When such a circuit is applied to a micro-patterned CMOS-LSI whose operation power supply is low in voltage, the SCR has to be triggered with a low voltage trigger so as to protect a MOS transistor having a low gate breakdown voltage. Under the circumstances, an example in which an ESD protection circuit employing an SCR is applied to a CMOS-LSI of the low power supply voltage type is disclosed in “A Gate-Coupled PTLSCR/NTLSCR ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS IC's 1”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 1, JANUARY 1997.
FIG. 17 is an equivalent circuit diagram showing the main part of an ESD protection circuit connected to the input circuit of a CMOS-LSI, disclosed in the publication described above. In this example (Prior Art 1), the ESD protection circuit employs an LVTSCR (Low-Voltage Triggered lateral SCR) as the SCR.
As shown in FIG. 17, a first ESD protection circuit 121 is connected between an input pad PAD, which is connected to internal circuits, and a VDD node to be supplied with a power supply potential VDD. A second ESD protection circuit 122 is connected between the input pad PAD and a ground potential VSS (GND).
In the first ESD protection circuit 121, the current passage between the anode and cathode of the LVTSCR1 used as a first SCR is connected between the VDD node and input pad PAD. The LVTSCR1 is arranged such that the base and collector of a PNP transistor Q1 are connected to the collector and base of an NPN transistor Q2, respectively. The emitter of PNP transistor Q1 comes to the anode, and the emitter of the NPN transistor Q2 comes to the cathode.
The current passage between the source S and drain D of a PMOS transistor Mp1 having a thin gate oxide film is connected between the VDD node and NPN transistor Q2. The gate G of the PMOS transistor Mp1 is connected to the VDD node.
A well layer resistance Rw1 exists from the base of the PNP transistor Q1 and the collector of the NPN transistor Q2 (N-Well) to the VDD node. A well layer resistance Rw2 exists between the emitter of the NPN transistor Q2 and the input pad PAD. A substrate resistance Rsub1 exists from the collector of the PNP transistor Q1 and the base of the NPN transistor Q2 (p-sub) to the GND.
In the second ESD protection circuit 122, the current passage between the anode and cathode of the LVTSCR2 used as a second SCR is connected between the input pad PAD and the GND. The LVTSCR2 is arranged such that the base and collector of a PNP transistor Q3 are connected to the collector and base of an NPN transistor Q4, respectively. The emitter of PNP transistor Q3 comes to the anode, and the emitter of the NPN transistor Q4 comes to the cathode.
The current passage between the drain D and source S of a NMOS transistor Mn1 having a thin gate oxide film is connected between the base of the PNP transistor Q3 and the emitter of the NPN transistor Q4. The gate G of the NMOS transistor Mn1 is connected to the GND.
A well layer resistance Rw3 exists from the base of the PNP transistor Q3 and the collector of the NPN transistor Q4 (N-Well) to the VDD node. A resistance Rw4 exists between the emitter of the NPN transistor Q4 and the GND. A substrate resistance Rsub2 exists between the base of the NPN transistor Q4 (the substrate region of the NMOS transistor TN) and the GND.
FIG. 18 is a sectional view schematically showing the LVTSCR2 as a representative of the LVTSCR1 and LVTSCR2 shown in FIG. 17.
As shown in FIG. 18, an N-well layer (N-Well) 131 is formed in the surface of a P-substrate (P-Substrate) 130. A P+-region (the emitter region of the PNP transistor Q3) 132 and an N+-region (the lead-out region of the N-well layer) 133 are formed adjacent to each other in the surface of the N-well layer (the base region of the PNP transistor Q3) 131. The P+-region 132 and N+-region 133 come to the anode of the LVTSCR (Anode).
An N+-region (the collector region of the NPN transistor Q4 and the drain region of the NMOSFET) 135 is formed in the surface including the interface between the N-well layer 131 and the P-substrate (the collector region of the PNP transistor Q3 and the base region of the NPN transistor Q4) 130. A device isolation region 134 is formed between the N+-region 135 and P+-region 132.
An N+-region (the emitter region of the NPN transistor Q4 and the source region of the NMOS transistor Mn1) 136 is formed adjacent to the N+-region 135 in the surface of the P-substrate 130. The N+-region 136 comes to the cathode of the LVTSCR (Cathode).
The gate electrode 137 of the NMOS transistor Mn1 is disposed, through a thin gate oxide film, on a channel region between the two N+-regions 135 and 136. The gate electrode 137 is connected to the cathode (the N+-region 136).
In the LVTSCR2 described above, both the PNP transistor Q3 and NPN transistor Q4 use the junction between the P-substrate 130 and N-well layer 131. It is specific that the drain region 135 of the NMOSFET is formed on a part of the junction.
The second ESD protection circuit 122 shown in FIG. 17, which employs the LVTSCR2 with the arrangement described above, operates as follows, when the input pad PAD receives a positive surge voltage. Specifically, if a voltage higher than a snap-back breakdown voltage is applied to the LVTSCR2 due to the surge voltage, the LVTSCR2 is turned on, using the snap-back current as a base current. As a consequence, the surge current is discharged to the GND, thereby protecting the input gate of the input circuit. However, if the voltage applied to the LVTSCR2, which is higher than a snap-back breakdown voltage, is higher than the gate breakdown voltage of the NMOS transistor Mn1, the internal circuits may be damaged by the surge voltage input.
FIG. 19 is an equivalent circuit diagram showing the main part of another ESD protection circuit, disclosed in the publication described above. In this example (Prior Art 2), the ESD protection circuit employs a lateral SCR, which uses a gate coupling technique and can be triggered with a still lower voltage.
As shown in FIG. 19, there is a first ESD protection circuit 151 different from the first ESD protection circuit 121 shown in FIG. 17, in the following points (1) to (4).
(1) In place of LVTSCR1 shown in FIG. 17, one PTLSCR (PMOS-Triggered lateral SCR) is used.
(2) The current passage between the source and drain of a PMOS transistor Mp1 is connected in parallel between a VDD node and the gate node of the PTLSCR (the base of an NPN transistor Q2).
(3) A resistance element Rp is connected between the VDD node and the gate of the PMOS transistor Mp1.
(4) A capacitance element Cp is connected between the gate of the PMOS transistor Mp1 and an input pad PAD.
Furthermore, there is a second ESD protection circuit 152 different from the second ESD protection circuit 122 shown in FIG. 17, in the following points (1) to (4).
(1) In place of LVTSCR2 shown in FIG. 17, one NTLSCR (NMOS-Triggered lateral SCR) is used.
(2) The current passage between the drain and source of an NMOS transistor Mn1 is connected in parallel between the gate node of the NTLSCR (the base of a PNP transistor Q3) and a cathode (the emitter of an NPN transistor Q4).
(3) A capacitance element Cn is connected between an input pad PAD and the gate of the NMOS transistor Mn1.
(4) A resistance element Rn is connected between the gate of the NMOS transistor Mn1 and a GND.
In the arrangement described above, the first ESD protection circuit 151 employing the PTLSCR operates, when the input pad PAD receives a negative surge voltage, such that the PMOS transistor Mp1 is transitionally turned on and inputs a trigger into the PTLSCR. As a consequence, the surge current flows to the VDD node, thereby protecting the input gate of the input circuit. In this case, the PMOS transistor Mp1 is turned back to the off-state in a predetermined delay time determined by the resistance element Rp and capacitance element Cp.
On the other hand, the second ESD protection circuit 152 employing the NTLSCR operates, when the input pad PAD receives a positive surge voltage, such that the NMOS transistor Mn1 is transitionally turned on and inputs a trigger into the NTLSCR. As a consequence, the surge current flows to the GND, thereby protecting the input gate of the input circuit. In this case, the NMOS transistor Mn1 is turned back to the off-state in a predetermined delay time determined by the capacitance element Cn and resistance element Rn.
As described above, the conventional ESD protection circuit employing an SCR pulls the trigger by utilizing a transitional potential change caused when an input pad connected to the SCR receives a surge voltage. This does not necessarily provide a good protection characteristic. When an ESD protection circuit employing an SCR is applied to an LSI having a low power supply voltage, it is preferable to realize a good protection characteristic with a low voltage trigger, thereby improving the reliability.